QEC decoding converges as DARPA narrows fault-tolerance race to four players

Surface code logical state teleportation demonstrated on superconducting processor.

• Teleportation of surface code logical states — not just individual physical qubits — was demonstrated on a superconducting processor and published in Nature Physics, satisfying a higher peer-review bar than most recent quantum milestones.
• The result is directly relevant to fault-tolerant architectures: logical state teleportation is a required primitive for many proposed fault-tolerant gate schemes, including lattice surgery, and showing it works on encoded multi-qubit states is a non-trivial advance.
• The superconducting platform origin keeps IBM and Google's hardware lineages most directly implicated as beneficiaries of this foundational capability.
• No commercial entity is named as author, suggesting this is academic progress that multiple hardware vendors could build upon rather than a proprietary competitive moat.

Source: Nature Physics

DARPA advances Atom Computing, Diraq, IBM, IonQ to program finals.

• DARPA has formally advanced Atom Computing, Diraq, IBM, and IonQ to the final stage of what is now confirmed as the Quantum Benchmarking Initiative (QBI), representing the U.S. government's clearest public statement yet on which hardware platforms it considers credible fault-tolerance candidates.
• The selection spans three qubit modalities — neutral atom (Atom Computing), spin/silicon (Diraq), superconducting (IBM), and trapped ion (IonQ) — suggesting DARPA is deliberately hedging across physical implementations rather than picking a single winner.
• Aalto University spinout Coherence Quantum's €2.78M seed raise for cryogenic hardware is a minor but real data point: the cryogenic control stack is increasingly attracting early-stage capital as a bottleneck investors are willing to bet on.
• For IonQ specifically, DARPA Stage C advancement provides a meaningful government validation signal at a time when the company faces ongoing scrutiny over near-term commercial revenue timelines.

Source: Google Alert — Atom Computing

IBM-Rutgers demo real-time 100-qubit feedback; DARPA QBI Stage C advances

• IBM and Rutgers demonstrated real-time quantum feedback control across 100 qubits, a scale at which classical control latency and bandwidth become genuine engineering constraints — making this a systems-level result, not just a qubit-count headline.
• Real-time feedback at this scale is a prerequisite for surface code error correction cycles, where syndrome measurements must be decoded and acted upon within the qubit coherence window; demonstrating it at 100 qubits narrows the gap to fault-tolerant operation.
• The simultaneous confirmation of IBM's DARPA Stage C advancement in the same news cycle reinforces IBM's position as arguably the most validated superconducting platform in the government's fault-tolerance program.
• No error rates or latency figures are disclosed in available summaries, which limits the ability to benchmark this result against SEEQC-NVIDIA's quantified gains reported the same day.

Source: Google Alert — Atom Computing

SEEQC+NVIDIA cut QEC latency and logical errors ~50%

• SEEQC's on-chip pre-decoder combined with NVIDIA's Ising AI decoding model simultaneously reduced decoding latency and logical error rates by approximately 50%, which is a rare result: most optimizations trade one for the other.
• The architecture is a hybrid multi-stage pipeline — classical digital logic on-chip handles initial filtering, then NVIDIA GPU runs the heavier AI inference — which mirrors the control-stack consolidation trend and positions NVIDIA as infrastructure for QEC, not just AI.
• Halving logical error rates has compounding value: error rates in surface codes scale exponentially with code distance, so linear improvements in physical or logical error rates translate to significant reductions in required overhead qubit counts.
• The result is reported as a company announcement rather than a peer-reviewed publication, so independent reproduction and methodology scrutiny are pending.

Source: Google Alert — SEEQC

NVIDIA GPU-optimized QEC decoder achieves low latency via CUDA Graphs.

• An arXiv preprint presents a GPU-optimized QEC decoder combining relay belief propagation with ordered statistics post-processing, using CUDA Graphs to minimize kernel launch overhead and achieve low-latency execution — a concrete software engineering contribution, not just an algorithmic one.
• CUDA Graphs specifically enable pre-compiled GPU execution pipelines, reducing the microsecond-level scheduling overhead that would otherwise make GPU decoders too slow for real-time QEC feedback loops; this paper directly addresses that known objection.
• The result corroborates and extends the SEEQC-NVIDIA announcement on the same day, suggesting NVIDIA's hardware is becoming the de facto standard platform for QEC decoding research regardless of qubit modality.
• As a preprint without peer review, latency and accuracy claims require independent validation, but the use of CUDA Graphs is a verifiable engineering choice with well-understood performance characteristics.

Source: arXiv quant-ph (RSS)

Peer critique challenges validity of Microsoft's Majorana gap protocol.

• An updated critical comment on Microsoft Quantum's 2023 topological gap protocol paper argues the protocol uses inconsistent definitions of 'gap' and 'topological' and employs circular reasoning, directly challenging the evidentiary basis for Microsoft's claimed Majorana zero mode detection.
• This is not a new critique but an updated version, indicating the scientific debate is ongoing and unresolved — Microsoft has not published a definitive rebuttal that has closed the controversy.
• The practical investment implication is significant: Microsoft's topological qubit roadmap, including the Majorana 1 chip announced in early 2025, rests substantially on the validity of the gap protocol as proof of concept; if the protocol is methodologically flawed, the timeline and technical claims require reassessment.
• None of today's positive QEC or hardware results involve Microsoft, making this a day where every other major platform advanced while Microsoft's foundational claims face renewed peer scrutiny.

Source: arXiv quant-ph (RSS)

Duplicate aggregation of DARPA finalist and Postquant Labs news.

• This item is a duplicate aggregation of the DARPA QBI Stage C advancement news and adds no incremental information beyond item rss:2f80e7d24b7348ca.
• The bundled mention of Postquant Labs launching a quantum virtual machine for multi-hardware execution is a minor product note: hardware-agnostic execution layers are becoming commoditized at the software level, though Postquant's specific differentiation is unclear from available detail.

Source: Google Alert — Atom Computing

SEEQC and NVIDIA combine chip pre-decoder with AI for better QEC.

• This is a press-release-level restatement of the SEEQC-NVIDIA QEC result covered in rss:b51f192e33b790cd; the chip-plus-GPU hybrid decoding architecture is confirmed as the core technical claim.
• The multi-stage decoding framing — on-chip pre-decoder filtering uncertain cases before GPU inference — is the key architectural detail worth tracking as a potential industry design pattern.

Source: The Quantum Insider

RhymeQ raises $2.2M for Python-native quantum programming

• RhymeQ's $2.2M seed raise targets Python-native quantum programming, addressing the developer tooling layer where friction remains high for non-specialist users.
• The funding size is pre-product-market-fit scale; notable primarily as a signal that investors see developer experience as an underserved market segment distinct from hardware and algorithms.

Source: Google Alert — SEEQC

AWS blog details NVIDIA Ising QEC decoding integration

• AWS published a diagram-level technical walkthrough of NVIDIA Ising decoding integration within the Braket QEC workflow, adding implementation detail to the broader NVIDIA-as-QEC-infrastructure narrative.
• The involvement of IQM Quantum Computers in this AWS-NVIDIA integration is a notable detail: it suggests the NVIDIA decoding stack is being validated across multiple qubit hardware vendors, not just SEEQC or IBM-adjacent systems.

D-Wave annealers used to simulate antiferromagnet magnetic reversal.

• D-Wave annealers were used to simulate antiferromagnet magnetic hysteresis, with researchers successfully extracting the Néel order parameter — a legitimate condensed matter physics use case for annealing hardware.
• This reinforces D-Wave's positioning as a near-term useful quantum device for specific simulation tasks, though it does not address the company's longer-term relevance as gate-based competitors scale.

Source: Google Alert — D-Wave

Lazarus group weaponizes NIST PQC standard ML-KEM in malware.

• Kaspersky reports Lazarus Group is embedding NIST-approved ML-KEM into malware delivery infrastructure, exploiting the algorithm's cryptographic complexity as an obfuscation layer against detection heuristics.
• This is the first reported nation-state weaponization of a finalized NIST PQC standard, creating an early operational security case study for enterprises evaluating PQC migration timelines.

Source: Google Alert — NIST quantum

Spin-based Kerr-cat qubit encoding proposed using quadrupolar nuclei.

• A theoretical preprint extends Kerr-cat qubit noise-bias concepts to quadrupolar nuclear spin systems near clock transitions, proposing suppression of both charge and magnetic noise in a single encoding.
• The work expands the cat-qubit design space beyond superconducting circuits but is entirely theoretical; experimental validation on this platform is not yet reported.

Source: arXiv quant-ph (RSS)

Qblox achieves sub-4 µs hybrid quantum-classical latency with NVIDIA DGX.

• Qblox achieved sub-4 µs roundtrip hybrid quantum-classical latency by integrating NVIDIA DGX Spark via NVQLink on RTX PRO 6000 Blackwell hardware — a latency figure within the range required for surface code syndrome-decode-feedback cycles on many qubit types.
• This is a vendor press release without peer-reviewed validation, but the NVQLink interconnect detail is specific enough to be technically meaningful: it implies GPU memory bandwidth, not just compute, is being leveraged for the feedback loop.

Source: The Quantum Insider

FAU and D-Wave launch $20M quantum supercomputer campus initiative.

• Florida Atlantic University and D-Wave are launching a $20M quantum supercomputer campus initiative in Palm Beach County, representing a regional hub-building strategy anchored by a university deployment.
• D-Wave's HQ relocation to Boca Raton (reported separately at 2★) suggests the company is deliberately building geographic density in South Florida, potentially leveraging state economic development incentives.

Source: Google Alert — D-Wave

AI reportedly breaks NIST PQC candidate HAWK cheaply

• A blog post claims AI cracked HAWK, a NIST post-quantum signature candidate, in 60 hours at approximately $100K compute cost — if accurate, a significant cryptanalytic result, though HAWK was not selected in NIST's finalized PQC standards.
• The source is a single blog post without peer-reviewed or conference backing; the claim warrants tracking but should not be treated as validated until independently confirmed.

Source: Google Alert — NIST quantum

Lazarus malware hides behind NIST-approved PQC algorithm

• A second independent source corroborates Lazarus Group's use of a NIST-approved PQC key encapsulation mechanism to obscure malware, elevating confidence in the underlying report beyond a single-vendor claim.
• The security operations implication is that PQC algorithm complexity can be adversarially exploited for obfuscation even before quantum computers threaten classical cryptography — a dimension of PQC deployment risk that enterprise security teams have not widely addressed.

SEEQC digital control speeds quantum error correction decoding

• This article provides incremental context on SEEQC's digital quantum control approach, referencing prior Nature Electronics results showing gate fidelities above 99.9% as the baseline from which the NVIDIA collaboration's decoding improvements are measured.
• No new technical content beyond the main SEEQC-NVIDIA announcement; useful as confirmation of the fidelity baseline underlying the decoding claims.

Source: Google Alert — SEEQC

SEEQC-NVIDIA QEC press release on Yahoo Finance

• This is the primary SEEQC-NVIDIA press release as distributed via Yahoo Finance, adding official corporate framing without incremental technical content beyond rss:b51f192e33b790cd.
• The Yahoo Finance distribution venue confirms this is being positioned for investor audiences, not just technical communities.

Source: Google Alert — SEEQC

Oxford spinout QuantrolOx raises £10M Series A

• QuantrolOx, an Oxford spinout focused on AI-driven autonomous qubit calibration, raised £10M (~$12.5M) Series A led by IW Capital — a meaningful funding round for the control and calibration infrastructure layer.
• Automated qubit tuning is a scaling bottleneck that grows superlinearly with qubit count; investor willingness to fund this layer at Series A scale suggests the market is maturing beyond pure hardware bets.

Neural frontend claims 100x faster quantum error decoding.

• CoDecoder proposes routing only uncertain measurement shots to a full decoder using a neural network frontend, claiming up to 100x speedup in mean decoding time — a result that would be practically transformative if it holds under peer review.
• The composability claim — that CoDecoder can front-end any existing decoder including belief propagation variants — is the key commercial appeal, as it would not require replacing deployed decoding infrastructure.

Source: arXiv quant-ph (RSS)

Bias-preserving entanglement demonstrated for Kerr-cat qubits.

• Researchers demonstrated bias-preserving entangling gates for Kerr-cat qubits using an ATS coupler, maintaining exponential bit-flip suppression through two-qubit operations — a critical requirement for any cat-qubit fault-tolerant architecture.
• This is directly relevant to Alice & Bob's commercial roadmap, which depends on demonstrating that cat-qubit noise bias can be preserved at the logical gate level, not just in isolated qubits.

Source: arXiv quant-ph (RSS)

New fault-tolerant architecture uses high-rate concatenated codes.

• A theoretical architecture proposal uses concatenated high-rate self-dual CSS codes with magic state injection to achieve parallel universal fault-tolerant logic, targeting lower resource overhead than standard surface code approaches.
• High-rate codes are an active area of competition with surface codes for resource efficiency; this paper adds to a growing body of alternatives that could reduce the qubit counts required for fault-tolerant computation by meaningful factors.

Source: arXiv quant-ph (RSS)

Evolutionary algorithm reduces latency in BP+OSD quantum decoders.

• An evolutionary algorithm is applied to optimize the belief propagation stage of BP+OSD decoders, reducing iteration count and latency — incremental improvement on a widely used decoding pipeline.
• The practical value is modest but real: BP+OSD is a leading decoder for LDPC codes, which are increasingly favored over surface codes for their superior rate, so efficiency gains here have broad applicability.

Source: arXiv quant-ph (RSS)

High-fidelity NV-center qubit tomography demonstrated at room temperature.

• High-fidelity quantum state tomography of a single NV-center using photoelectric readout at room temperature is reported, with competitive gate fidelity — relevant as a proof-of-concept for diamond-based qubits avoiding cryogenic requirements.
• Scalability from single NV-centers to multi-qubit arrays remains the fundamental unsolved problem for this platform; room-temperature operation advantage is real but insufficient alone to drive near-term commercial relevance.

Source: arXiv quant-ph (RSS)

Silicon photonics chip demonstrated for compact QKD transmitters.

• A silicon photonics-integrated QKD transmitter chip is demonstrated, reducing bulk and cost compared to rack-mounted alternatives — a necessary step toward practical fiber and eventually satellite QKD deployment.
• Photonic integration for QKD is at a different technology readiness level than fault-tolerant compute; this result is meaningful for the quantum networking segment but does not directly accelerate the compute roadmap.

Source: arXiv quant-ph (RSS)

Dynamic T-state factory scheduling proposed to cut fault-tolerant overhead.

• Dynamic T-state post-selection and budget-aware factory provisioning are proposed to reduce magic state overhead in surface code fault-tolerant computation — directly targeting one of the largest known resource cost drivers in the leading fault-tolerance architecture.
• Reducing T-factory overhead has direct implications for the physical qubit counts required for practical fault-tolerant algorithms; any validated reduction here compresses timeline estimates for commercially relevant quantum advantage.

Source: arXiv quant-ph (RSS)